The present invention relates to a method for driving a plasma display panel (PDP) and a PDP device. More particularly, the present invention relates to a driving method that improves the display contrast of a PDP.
FIG. 1 is a diagram showing a basic configuration of a PDP device.
A plasma display panel (PDP) 1 is a device that performs display by causing a discharge to occur in a discharge space sandwiched by two glass substrates with a mixture of a neon gas, a xenon gas, etc., by applying a voltage greater than a discharge start voltage between electrodes formed on the substrate, and exciting phosphors, formed on the substrate, so that they emit light, using ultraviolet rays generated by the discharge. Although various configurations have been proposed for a PDP, a three-electrode surface discharge type panel, which is currently most widely put to use, is described as an example.
In the plasma display panel (PDP) 1, plural X electrodes 2 (sustain electrodes) and Y electrodes 3 (scan electrodes) are arranged adjacently by turns and address electrodes 4 (third electrodes) are arranged in the direction perpendicular to that in which the X electrodes and the Y electrodes extend. Between a pair of X electrode and Y electrode, that is, between X1 and Y1, between X2 and Y2, . . . , a display line is formed and a display cell 5 is formed at the crossing of each display line and the address electrode 4. The X electrodes and the Y electrodes are referred to as display electrodes.
The X electrodes are commonly connected to an X drive circuit 7 and the same drive signal is applied to them. The X drive circuit 7 is provided with a sustain pulse circuit 8 that generates a sustain pulse, which will be described later, and a voltage used for resetting and addressing, and a reset/address voltage generation circuit 9. The Y electrodes are connected individually to a scan circuit 11 provided within a Y drive circuit 10, and a scan pulse is applied sequentially to them during an address period, which will be described later. The Y drive circuit 10 is further provided with a sustain pulse circuit 12 that generates a sustain pulse and a reset/address voltage and a reset/address voltage generation circuit 13. The address electrodes are connected to the address driver 6 and an address signal to select a cell to be lit or not lit is applied to them during addressing in synchronization with the scan pulse.
As a discharge in a PDP takes only two values, that is, ON and OFF, gradation is displayed by varying the number of times of light emission. Therefore, a frame that corresponds to a display of a screen is divided into plural subfields. Each subfield is composed of an initialization period (reset period), an address period and a sustain discharge period (sustain period). During the initialization period, addressing is performed so that all the display cells are put into a uniform state in which, for example, wall charges are erased, or wall charges are formed uniformly, regardless of the lit or unlit state of the cells in the previous subfield. During the address period, a selective discharge (address discharge) is caused to occur so that the ON (lit) or OFF (unlit) state of a display cell is determined according to display data and the wall charges in a cell to be lit are put into a state different from that of a cell not to be lit. During the sustain discharge period, a discharge is caused to occur repeatedly in a display cell selected during the address period and light is emitted. If the number of sustain discharge pulses, that is, the period of the sustain discharge pulse, is constant, the length of a sustain discharge period differs from subfield to subfield, therefore gradation is expressed by setting the ratio of times of light emission in each subfield to, for example, 1:2:4:8: . . . , and combining subfields that emit light according to the gradation of each display cell.
FIG. 3 is a diagram that shows typical examples of drive waveforms of conventional PDP devices. As shown schematically, an initialization period TR is composed of a charge write period TR1 and a charge adjust period TR2. In the charge write period TR1, in a state in which 0V is being applied to the address electrode A, an inclined wave-shaped pulse, the voltage of which varies gradually from 0V to Vw, is applied to the Y electrode, and an inclined wave-shaped pulse, the voltage of which gradually varies from 0V to Vq, is applied to the X electrode. Due to this, a discharge is caused to occur everywhere regardless of the wall charges accumulated in the display cells, and negative wall charges are accumulated on the Y electrode and the positive charges, on the X electrode. During the charge adjust period TR2, a inclined wave-shaped pulse, the voltage of which varies gradually from Vw to Vry, is applied to the Y electrode and a voltage Vx is applied to the X electrode, therefore, the wall charges accumulated in the Y electrode and X electrode during the TR1 period decrease almost to zero. There may be some cases where a certain amount of charge, with which a discharge is not caused to occur even if a sustain discharge pulse is applied, is left on the Y electrode and X electrode.
During the address period TA, the voltage Vx is applied to the X electrode and, in a state in which 0V is being applied to the Y electrode, a scan pulse having the voltage Vy is applied sequentially to the Y electrode and an address voltage Va is applied to the address electrode A in a cell to be lit in synchronization with the application of the scan pulse. The voltage 0V is applied to the address electrode in a cell not to be lit. An address discharge is caused to occur in a cell to be lit to which the scan pulse and the address voltage have been applied, and positive wall charges are accumulated on the Y electrode and negative charges are accumulated on the X electrode. These wall charges on the Y electrode and X electrode are able to cause a sustain discharge to occur when a sustain discharge pulse is applied. As an address discharge is not caused to occur in a cell not to be lit, the amount of wall charges on the Y electrode and X electrode remains almost zero.
During the sustain discharge period TS, in a state in which 0V is being applied to the address electrode, a voltage Vs1 and the voltage 0V are applied alternately to the X electrode and Y electrode as a sustain discharge pulse. In a cell to be lit, the voltage due to wall charges is added to the voltage of the sustain discharge pulse, the discharge start voltage is exceeded, a sustain discharge is caused to occur, and the charges move and an amount of charges necessary for the next sustain discharge is accumulated on the Y electrode and X electrode. In other words, when the address period is completed, positive wall charges are accumulated on the Y electrode and negative wall charges are accumulated on the X electrode, that is, a voltage, the high potential side of which is the Y electrode, is being applied between the Y electrode and the X electrode. Therefore, if the voltage Vs1 is applied to the Y electrode and 0V is applied to the X electrode as a sustain discharge pulse at the inception of the sustain discharge period, the voltage due to the above-mentioned wall charges are added, the discharge start voltage is exceeded, and a sustain discharge is caused to occur. When a sustain discharge is caused to occur, the positive charges move from the Y electrode to the X electrode and accumulate thereon, the negative charges move from the X electrode to the Y electrode and accumulate thereon, and the sustain discharge is terminated because a voltage, the high potential side of which is the X electrode, is produced. Then, if 0V applied to the Y electrode and a voltage Vs is applied to the X electrode as a sustain discharge pulse, a sustain discharge is caused to occur because the voltage due to the wall charges, the high potential side of which is the X electrode, is added. This cycle is repeated during the sustain discharge period. As no charge is accumulated in a cell not to be lit, no discharge is caused to occur even though a sustain discharge pulse is applied to either electrode.
FIG. 4 is a diagram that shows other examples of drive waveforms of conventional PDP devices. These examples differ from those in FIG. 3 in that a sustain discharge pulse is composed of positive pulses and negative pulses, the absolute value of voltage of which is Vs, that the final voltage of an inclined wave-shaped pulse to be applied to the X electrode during TR1 is −Vs, and that the voltage of the scan pulse is −Vs. The operations are almost the same as the examples in FIG. 3. In the examples in FIG. 4, the number of power sources can be reduced because the voltage Vs is used commonly, therefore, the advantage that the cost will be reduced can be gained. In the examples in FIG. 4, Vs is 70 to 90V, Vw, 150 to 200V, Vx, 110 to 140V, Vry, −Vs to (−Vs+20V), and Va, 50 to 70V.
The typical conventional PDP devices are described above, but there are various kinds of methods for driving PDP devices. For example, in Japanese Patent No 2801893, an ALIS method PDP device, in which the number of display lines can be doubled while the number of display electrodes remains the same as before by utilizing every gap between adjacent X electrodes and Y electrodes as a display line, has been disclosed. As the PDP device is widely known, a detailed description is not given here.
An address method performed during the above-mentioned address period includes a write address method and an erase address method. The write address method is a method in which wall charges necessary for a sustain discharge are formed by causing an address discharge to occur in a cell to be lit during the address period, and the drive methods shown in FIG. 3 and FIG. 4 employ the write address method. The write address method includes a case where wall charges are decreased to zero during the initialization period and another case where a certain amount of wall charge is left. If the wall charges are decreased to zero, the margin where light is not emitted in a cell not to be lit during the sustain discharge period becomes the largest, but problems occur such as that the voltage of the scan pulse needs to be raised because it is more unlikely that an address discharge is caused to occur. On the other hand, when a certain amount of wall charge is left, advantages are gained such as that the voltage of a scan pulse can be lowered, but the margin where light is not emitted in a cell not to be lit during the sustain discharge period becomes small.
Either way, in the conventional write address method, it is necessary to form wall charges while applying a scan pulse and, therefore, the width of the scan pulse needs to be lengthened to a certain extent, resulting in a problem that the address period is lengthened accordingly.
On the other hand, the erase address method is a method in which wall charges are formed in all of the display cells during the initialization period and the wall charges in a cell not to be lit are erased and those in a cell to be lit are left during the address period. In this method also, there are two cases where the wall charges in a cell not to be lit are erased completely and where a certain amount of wall charges is left, and this method has both advantages and disadvantages as a write address method.
Japanese Patent Application No. 2000-336248 (Japanese Unexamined Patent Publication (Kokai) No. 2002-140033: disclosed May 17, 2002) has disclosed an erase address method, in which an erase period during which wall charges in a cell not to be lit are erased and a write period during which wall charges necessary for a sustain discharge are formed in a cell to be lit are provided, after the wall charges in the cell not to be lit are erased to a certain extent during the select period.
Moreover, Japanese Unexamined Patent Publication (Kokai) No. 11-327505 has disclosed a structure, in which charges in a cell to be lit are adjusted after an address period, in an ALIS method PDP disclosed in the above-mentioned Japanese Patent No. 2801893.
The present invention relates to a write address method.
One of the factors that determine the picture quality of a display device is contrast, and what deteriorates the contrast most is a background light emission in an unlit state. A light emission caused by a discharge during the initialization period TR is a light emission that has no relationship with display data and can be a factor to deteriorate the contrast and the picture quality.
There can be thought two ways which will reduce the intensity of a light emission caused by a discharge during the initialization period TR, as follows:
(1) The application voltage during the charge write period TR1 is reduced; or
(2) The slope with which the voltage varies during the charge write period TR1 or the charge adjust period TR2 is made to be more gradual.
However, the step (1) brings a problem that an initialization malfunction, in which no discharge is caused to occur in some display cells depending on the previous display state, is brought about and the margin of operation may be deteriorated. The step (2) brings a problem that the drive time is protracted. Therefore, the above-mentioned steps (1) and (2) are limited in reducing the background light emission.
In the conventional drive methods shown in FIG. 3 and FIG. 4, the voltage to be applied between the X electrode and the Y electrode during the charge adjust period TR2 is made to be almost equal to or slightly less than the voltage to be applied between the X electrode and the Y electrode during the address period TA. This is because a problem occurs that an erroneous discharge is caused to occur in a cell not to be lit when the voltage to be applied between the X electrode and the Y electrode during TR2 is much less than the voltage to be applied between the X electrode and the Y electrode during TA, and when, contrary to this, the former voltage is much greater than the latter one, another problem occurs that a wasteful background light emission is caused to occur during TR2. Moreover, as it is necessary to accumulate an amount of charge sufficient to cause a discharge to occur in a cell to be lit by applying a sustain discharge pulse during the address period TA, the voltage to be applied between the X electrode and the Y electrode needs to be increased. However, if the voltage to be applied between the X electrode and the Y electrode is increased during the address period TA, it is also necessary to increase the application voltage during the charge adjust period TR2 because of the above-mentioned reasons, therefore, the background light emission cannot be reduced during TR2. Therefore, a new drive method that can reduce the background light emission and improve contrast is required.